1. Field of the Invention
The present invention relates to substrate processing, and more particularly to improving the process yield using hot-spot procedures and data.
2. Description of the Related Art
Many multiple patterning techniques are currently being use during semiconductor substrate processing to increase the number of features and/or structures within devices on a substrate. Multiple patterning techniques can include double exposure techniques, double patterning techniques, spacer techniques, mask techniques, and brute force techniques. In 2006, the International Technology Roadmap for Semiconductors roadmap was expanded to include double patterning a potential solution for 32 nm lithography. Multiple patterning techniques are viewed as some device manufacturers as bridge solutions that can be used until Extreme Ultra-Violet (EUV) techniques become more fully developed.
Integrated Circuit (IC) design shrinks push the limits of lithography resolution. Chemical processes become more sensitive to defects or patterning errors when pushed to the lithography limits. IC manufactures have historically used lithography simulations and CD SEM measurements to determine the focus and dose latitude as a means to determine design rules. Optical proximity correction for mask sizing is typically driving by CD SEM measurements for absolute dimensional targeting. In addition, yield enhancement is currently being performed using defect inspection tools that are typically separated from the lithography simulation based techniques that are used for mask at each IC layer.